High-precision analog-to-digital converter and dnl-based  performance improvement method

ABSTRACT

The present invention provides a high-precision analog-to-digital converter, includes a redundant weight capacitor array, a comparator, a code reestablishment circuit, a weight storage circuit and a control logic circuit. The redundant weight capacitor array collects input voltages and generates output voltages in a sampling stage. The comparator compares the output voltages of the redundant weight capacitor array. The code reestablishment circuit calculates an output code of the successive approximation type analog-to-digital converter according to the comparator output result and a capacitor weight in the weight storage circuit. The weight storage circuit stores the capacitor weight. The control logic circuit controls the sampling and conversion stages of the redundant weight capacitor array. The present invention also provides a DNL-based performance improvement method adapted to the analog-to-digital converter.

BACKGROUND OF THE INVENTION Technical Field

The present invention belongs to the technical field ofanalog-to-digital converters, and in particular to a high-precisionanalog-to-digital converter and a DNL-based performance improvementmethod.

Description of Related Art

A successive approximation type analog-to-digital (A/D) convertertypically comprises a comparator, a capacitor array, a successiveapproximation register and a control logic circuit, with most of thesecircuit modules being digital circuits; and therefore, with thereduction of a technological dimension, the successive approximationtype A/D converter starts to demonstrate an innate structural advantagethereof, where the digital circuit is not only faster in speed and lowerin power consumption, but also smaller in area along with the reductionof the technological dimension, and this is in line with therequirements for low power consumption and miniaturization of a modernelectronic product. Of course, an analog circuit therein also faces theproblem of gain reduction and power consumption increase brought by thereduction of the technological dimension, but the advantage outweighsits disadvantage from a comprehensive view. Therefore, a successiveapproximation type structure becomes an international research hotspotin recent years.

The research on the successive approximation type A/D converter atpresent mainly focuses on the low-medium precision, and the research onthe high precision is relatively scant, with the reason that a mismatcherror of a capacitor array results in the linearity reduction and signalto noise ratio reduction of a high-precision successive type A/Dconverter due to the presence of a process variation, therefore, themismatch error of the capacitor array becomes a key limiting factorrestricting the performance of the high-precision successive type A/Dconverter. Based on studies, the inventor of the present invention hasfound that when a traditional capacitor array mismatch error measurementand correction method for the successive approximation type A/Dconverter is applied to the high-precision successive approximation typeA/D converter, there are the following problems.

1. Structural Problem:

In a successive approximation type A/D converter of a traditionalstructure, if a digital correction method is adopted to record an actualweight of each capacitor, a code missing phenomenon may occur when ahigh bit weight is more than a sum of all the residual bit weights plus1LSB (Least Significant Bit), even though the actual weight of eachcapacitor can be measured correctly. For example, a 4-bit A/D converterhas an actual weight of (9, 3, 2, 1), with an input output correspondingrelation as follows:

Input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Output 0 1 2 3 4 5 6 6 6 910 11 12 13 14 15

It follows that 7 and 8 in an output code are missing. Therefore, forthe successive approximation type A/D converter of the traditionalstructure, the digital method cannot be used for correcting thecapacitor mismatch error.

2. Problem on Mismatch Error Measurement:

For the traditional measurement of the capacitor mismatch error, a smallcapacitor array is typically introduced for assistance, meanwhile, acorresponding control switch and a corresponding control logic circuitare required, which not only increases the complexity of a circuitdesign but also results in the measurement precision reduction of thecapacitor mismatch error since the introduced small capacitor arraylikewise has a capacitor mismatch error, and it is very difficult tomeet the requirement on measurement precision during application to thehigh-precision successive approximation type A/D converter.

3. Problem on Capacitor Mismatch Error Correction:

With the traditional correction method for the capacitor mismatch error,a compensating capacitor array is typically used to compensate thecapacitor mismatch error; when a certain capacitor participates in anaddition and subtraction operation of a charge, a correspondingcompensating capacitor array compensates a charge change caused by themismatch error thereof; since the compensation precision must be within1LSB, the compensating capacitor array must employ a complex structureto implement high compensation precision when the precision of thesuccessive approximation type A/D converter increases, therefore, it isvery difficult to implement the compensating capacitor array.

BRIEF SUMMARY OF THE INVENTION

Specific to the technical problems existing in the prior art, thepresent invention provides a high-precision successive approximationtype analog-to-digital converter, which effectively reduces thecomplexity of a circuit design and may accurately measure a capacitormismatch error and perform capacitor mismatch error correction withoutan auxiliary capacitor array, an auxiliary switch and a control logic,thereby achieving the object of promoting the signal to noise ratio,linearity and conversion speed of the A/D converter.

To achieve the object as described above, a technical solution employedby the present invention is as follows:

A high-precision analog-to-digital converter, characterized bycomprising a redundant weight capacitor array, a comparator, a codereestablishment circuit, a weight storage circuit and a control logiccircuit; wherein

the redundant weight capacitor array receives external input voltagesVin+ and Vin−, generates output voltages Vout+ and Vout− under thecontrol of the control logic circuit, supplies the output voltages Vout+and Vout− to the comparator for comparison, and controls each bit ofcapacitor to participate in a voltage addition and subtraction operationin sequence under the control of the control logic circuit according toa comparison result of the comparator to regenerate output voltagesVout+ and Vout− which are supplied to the comparator for comparison,repeating as such until a last bit of capacitor completes the voltageaddition and subtraction operation, and the redundant weight capacitorarray is combined with the weight storage circuit to implement digitalcorrection of a capacitor mismatch error, thereby preventing codemissing for the analog-to-digital converter;

the comparator compares the output voltages Vout+ and Vout− of theredundant weight capacitor array, outputs 1 if Vout+ is more than Vout−,or else, outputs 0;

the code reestablishment circuit calculates an output code of thesuccessive approximation type analog-to-digital converter according toan output result of the comparator and an actual capacitor weightextracted according to DNL in the weight storage circuit;

the weight storage circuit stores the actual capacitor weight extractedaccording to DNL; and

the control logic circuit controls the redundant weight capacitor arrayto collect the input voltages in a sampling stage and controls acorresponding weight capacitor of the redundant weight capacitor arrayto implement the voltage addition and subtraction operation according tothe output result of the comparator in a conversion stage.

The high-precision analog-to-digital converter provided by the presentinvention employs a capacitor array with redundant weights to enable thedigital correction of a capacitor mismatch error, and with the use ofthe redundant weight, an error brought by the incomplete establishmentof the capacitor array can be withstood, thereby promoting theconversion speed of the analog-to-digital converter; and with themeasurement of the capacitor mismatch error in the present invention,the capacitor mismatch error can be measured without the auxiliarycapacitor array, the auxiliary switch and the control logic, therebyreducing the complexity of the circuit design, and saving layout areaand power consumption, meanwhile, with a digital method in the presentinvention for measuring and correcting the capacitor mismatch, the errormeasurement and correction precision is not limited by a technologicalcondition, thereby improving the measurement and correction precision,and the signal to noise ratio and linearity of the analog-to-digitalconverter are improved by measuring and correcting the capacitormismatch error.

Further, the redundant weight capacitor array comprises n bits ofeffective capacitors (corresponding to n effective weights) and at leastr bits of redundant capacitors (corresponding to r redundant weights),and the number of capacitors included in each bit of the effectivecapacitor and redundant capacitor is an integral multiple of 2, whereinan n^(th) bit of effective capacitor is C_(n), an (n−1)^(th) bit ofeffective capacitor is C_(n-1), . . . , a first bit of effectivecapacitor is C₁, C_(n) is a highest weight effective capacitor with theweight of W_(n), C₁ is a lowest weight effective capacitor with theweight of W₁; and an r^(th) bit of redundant capacitor is C′_(r), an(r−1)^(th) bit of redundant capacitor is C′_(r-1) . . . , a first bit ofredundant capacitor is C′₁, C′r is a highest weight redundant capacitorwith the weight of W′_(r), C′₁ is a lowest weight redundant capacitorwith the weight of W′₁, the redundant weight capacitor array maycomprise one or more bits of redundant capacitors from C′_(r), . . . ,C′₁ for analog-to-digital conversion, and at least one bit of redundantcapacitor is present at each redundant weight.

Further, the redundant capacitors are located behind the effectivecapacitors having the same weight as the redundant capacitors.

Further, a maximum capacitor mismatch error determined by a process anda circuit structure is N_(mismatch) _(_) _(max) LSB, and a minimumredundant weight number required by the redundant weight capacitor arrayis N_(r) _(_) _(min)=1+log₂(N_(mismatch) _(_) _(max)).

Further, the redundant weight capacitor array and the comparatorsimultaneously employ a differential structure for connection orsimultaneously employ a single-end structure for connection.

The present invention also provides a DNL-based performance improvementmethod, the method being adapted to the foregoing high-precisionsuccessive approximation type analog-to-digital converter, comprisingthe following steps:

Receiving external input voltages Vin+ and Vin− for sampling, generatingoutput voltages Vout+ and Vout− after sampling and supplying the outputvoltages Vout+ and Vout− to a comparator for comparison, by a redundantweight capacitor array;

comparing the output voltages Vout+ and Vout− by the comparator toobtain a comparison output result;

controlling a corresponding weight capacitor of the redundant weightcapacitor array according to the comparison output result to perform avoltage addition and subtraction operation, regenerating output voltagesVout+ and Vout− and supplying the output voltages Vout+ and Vout− to thecomparator for comparison, by a control logic circuit, repeating as suchuntil a lowest weight bit of capacitor completes the voltage additionand subtraction operation, and implementing digital correction for acapacitor mismatch error by the redundant weight capacitor array incombination with a weight storage circuit to prevent code missing forthe analog-to-digital converter; and

storing each comparison output result, reading an actual capacitorweight extracted according to DNL in the weight storage circuit andcalculating an output code of the successive approximation typeanalog-to-digital converter, by a code reestablishment circuit.

The DNL-based performance improvement method adapted to the foregoinghigh-precision successive approximation type analog-to-digital converterprovided by the present invention employs a capacitor array withredundant weights to enable the digital correction of the capacitormismatch error, and with the use of the redundant weight, an errorbrought by the incomplete establishment of the capacitor array can bewithstood, thereby promoting the conversion speed of theanalog-to-digital converter; and with the measurement of the capacitormismatch error in the present invention, the capacitor mismatch errorcan be measured without the auxiliary capacitor array, the auxiliaryswitch and the control logic, thereby reducing the complexity of thecircuit design, and saving layout area and power consumption, meanwhile,with a digital method in the present invention for measuring andcorrecting the capacitor mismatch, the error measurement and correctionprecision is not limited by a technological condition, thereby improvingthe measurement and correction precision, and the signal to noise ratioand linearity of the analog-to-digital converter are improved bymeasuring and correcting the capacitor mismatch error.

Further, after the redundant weight capacitor array performs sampling,the output voltage Vout+ is equal to βVin+, the output voltage Vout− isequal to βVin−, and the comparator compares a first output of the outputvoltages Vout+ and Vout− to obtain a comparison output result D_(n); thecontrol logic circuit controls an effective capacitor C_(n) to performthe voltage addition and subtraction operation according to thecomparison output result D_(n) to obtain a second output of Vout+ andVout−; and the comparator compares the a second output of the outputvoltages Vout+ and Vout− to obtain a comparison output result D_(n-1),repeating as such until a lowest weight bit of capacitor completes thevoltage addition and subtraction operation.

Further, if the comparison output result D_(n) is 1, an output voltageof the n^(th) effective capacitor after operation is

${\lbrack {( V_{{out} +} ) - ( V_{{out} -} )} \rbrack_{n} = {\lbrack {( V_{{out} +} ) - ( V_{{out} -} )} \rbrack_{0} - {\beta {Vref}\frac{W_{n}}{\sum\limits_{k = {i + 1}}^{n}W_{k}}}}};$

if the comparison output result D_(n) is 0, an output voltage of then^(th) effective capacitor after operation is

${\lbrack {( V_{{out} +} ) - ( V_{{out} -} )} \rbrack_{n} = {\lbrack {( V_{{out} +} ) - ( V_{{out} -} )} \rbrack_{0} - {\beta {Vref}\frac{W_{n}}{\sum\limits_{k = {i + 1}}^{n}W_{k}}}}};$

and C_(n), C_(n-1), . . . , C_(r), C′_(r), C_(r-1), C′_(r-1), . . . ,C₁, C′₁ sequentially perform the voltage addition and subtractionoperation in turn, wherein β is a ratio of a sum of sampling capacitorsto a sum of all the capacitors, i.e.,

$\beta = {\frac{\sum\limits_{k = {i + 1}}^{n}W_{k}}{{\sum\limits_{k = 1}^{n}C_{k}} + {\sum\limits_{k = 1}^{r}C_{k}^{\prime}}}.}$

Further, the code reestablishment circuit calculates the output code ofthe successive approximation type analog-to-digital converter with aformula as follows:

D _(out) =W _(n) D _(n) +W _(n-1) D _(n-1) + . . . +W _(r) D _(r) +W′_(r) D′ _(r) + . . . +W ₁ D ₁ +W ₁ D′ ₁,

wherein W_(n), W_(n-1), . . . , W_(r), W′_(r), . . . , W₁, W′₁ arecapacitor weights stored in the weight storage circuit, and D_(n),D_(n-1), . . . , D_(r), D′_(r), . . . , D₁, D′₁ are comparison outputresults of the comparator.

Further, the extracting of the actual capacitor weight extractedaccording to DNL, stored in the weight storage circuit, comprises thefollowing steps:

Setting a capacitor weight initial value in the weight storage circuitas an ideal weight;

turning off all the redundant capacitors and then performing A/Dconversion to obtain a first output sequence code of the codereestablishment circuit;

calculating a first DNL sequence of the analog-to-digital converteraccording to the first output sequence code;

extracting actual weights of effective capacitors according to the firstDNL sequence;

turning off the effective capacitors corresponding to all the redundantcapacitors and then performing A/D conversion to obtain a second outputsequence code of the code reestablishment circuit;

calculating a second DNL sequence of the analog-to-digital converteraccording to the second output sequence code; and

extracting actual weights of the redundant capacitors according to thesecond DNL sequence.

Further, the setting a capacitor weight initial value in the weightstorage circuit as an ideal weight specifically comprises:

Setting a significant bit weight, with a j^(th) significant bit weightW_(j)=2^(j-1), wherein j=1, 2, . . . , n; and

setting a redundant bit weight, with a k^(th) redundant bit weightW′_(k)=W_(k)=2^(k-1), wherein k=1, 2, . . . , r.

Further, the extracting actual weights of effective capacitors accordingto the first DNL sequence specifically comprises the following steps:

restoring according to the first DNL sequence to obtain an input outputrelation of the analog-to-digital converter as follows:

${{A_{m}(x)} = {{\sum\limits_{j = 1}^{x}{A(j)}} = {x + {\sum\limits_{j = 1}^{x}{{DNL}(j)}}}}},$

wherein A_(in)(x) is an analog input voltage increment corresponding toa digital code x;

extracting a weight of an n^(th) effective capacitor as follows:

${W_{n} = {\frac{1}{2^{n - 1} - {2{N_{e}(n)}}}\lbrack {{\sum\limits_{j = {2^{n - 1} + {N_{e}{(n)}}}}^{2^{n} - {N_{e}{(n)}}}{A_{in}(j)}} - {\sum\limits_{j = {N_{e}{(n)}}}^{2^{n - 1} - {N_{e}{(n)}}}{A_{in}(j)}}} \rbrack}},$

wherein N_(e)(n) is a number of rejection points determined by processmismatch; assuming a maximum mismatch determined by a process variationis e %, N_(e)(n) is a rounded product of 2″*e % in the calculation of ann^(th) bit of capacitor weight, i.e. N_(e)(n)=int(2n×e %);

extracting a weight W_(n-1) of an (n−1)^(th) bit of effective capacitoras follows:

$W_{{({n - 1})}_{1}} = {\frac{1}{2^{n - 2} - {2{N_{e}( {n - 1} )}}}\lbrack {{\sum\limits_{j = {2^{n - 2} + {N_{e}{({n - 1})}}}}^{2^{n - 1} - {N_{e}{({n - 1})}}}{A_{in}(j)}} - {\sum\limits_{j = {N_{e}{({n - 1})}}}^{2^{n - 2} - {N_{e}{({n - 1})}}}{A_{in}(j)}}} \rbrack}$$W_{{({n - 1})}_{2}} = {\frac{1}{2^{n - 2} - {2{N_{e}( {n - 1} )}}}\lbrack {{\sum\limits_{j = {2^{n - 2} + {N_{e}{({n - 1})}} + 2^{n - 1}}}^{2^{n - 1} - {N_{e}{({n - 1})}} + 2^{n - 1}}{A_{in}(j)}} - {\sum\limits_{j = {{N_{e}{({n - 1})}} + 2^{n - 1}}}^{2^{n - 2} - {N_{e}{({n - 1})}} + 2^{n - 1}}{A_{in}(j)}}} \rbrack}$$\mspace{20mu} {{W_{({n - 1})} = {\frac{1}{2}\lbrack {W_{{({n - 1})}_{1}} + W_{{({n - 1})}2}} \rbrack}},}$

wherein N_(e)(n−1)=int(2n⁻¹×e %); and

extracting a weight W_(m) of an m^(th) bit of effective capacitor asfollows:

$\mspace{20mu} {W_{m_{1}} = {\frac{1}{2^{m - 1} - {2{N_{e}(m)}}}\lbrack {{\sum\limits_{j = {2^{m - 1} + {N_{e}{(m)}}}}^{2^{m} - {N_{e}{(m)}}}{A_{in}(j)}} - {\sum\limits_{j = {N_{e}{(m)}}}^{2^{m - 1} - {N_{e}{(m)}}}{A_{in}(j)}}} \rbrack}}$$W_{m\; 2} = {\frac{1}{2^{m - 1} - {2{N_{e}(m)}}}\lbrack {{\sum\limits_{j = {2^{m - 1} + {N_{e}{(m)}} + 2^{m}}}^{2^{m} - {N_{e}{(m)}} + 2^{m}}{A_{in}(j)}} - {\sum\limits_{j = {{N_{e}{(m)}} + 2^{m}}}^{2^{m - 1} - {N_{e}{(m)}} + 2^{m}}{A_{in}(j)}}} \rbrack}$  …$W_{m_{(2^{n - m})}} = {\frac{1}{2^{m - 1} - {2{N_{e}(m)}}}{\quad {{{\lbrack {{\sum\limits_{j = {2^{m - 1} + {N_{e}{(m)}} + {{({2^{n - m} - 1})}2^{m}}}}^{2^{m} - {N_{e}{(m)}} + {{({2^{n - m} - 1})}2^{m}}}{A_{in}(j)}} - {\sum\limits_{j = {{N_{e}{(m)}} + {{({2^{n - m} - 1})}2^{m}}}}^{2^{m - 1} - {N_{e}{(m)}} + {{({2^{n - m} - 1})}2^{m}}}{A_{in}(j)}}} \rbrack \mspace{20mu} W_{m}} = {\frac{1}{2^{n - m}}{\sum\limits_{j = 1}^{2^{n - m}}W_{mj}}}};}}}$

repeating as such to extract all capacitor weights remained after them^(th) capacitor;

if the capacitor weights of the capacitors after the m^(th) capacitor asdetermined by the process variation have no effect on the monotonicityof the capacitor array, a mismatch error of a capacitor with the weightof less than W_(m) is negligible, and the weight of the capacitor is anideal weight.

Further, the extracting actual weights of the redundant capacitorsaccording to the second DNL sequence specifically comprises thefollowing steps:

Restoring according to the second DNL sequence to obtain an input outputrelation of the analog-to-digital converter as follows:

${{A_{in}^{\prime}(x)} = {{\sum\limits_{j = 1}^{x}{A^{\prime}(j)}} = {x + {\sum\limits_{j = 1}^{x}{{DNL}^{\prime}(j)}}}}},$

wherein A′_(in)(x) is an analog input voltage increment corresponding toa digital code x;

extracting a weight W_(r′) of an r′^(th) redundant capacitor as follows:

$\mspace{20mu} {W_{r_{1}^{\prime}} = {\frac{1}{2^{r^{\prime} - 1} - {2{N_{e}( r^{\prime} )}}}\lbrack {{\sum\limits_{j = {2^{r^{\prime} - 1} + {N_{e}{(r^{\prime})}}}}^{2^{r^{\prime}} - {N_{e}{(r^{\prime})}}}{A_{in}(j)}} - {\sum\limits_{j = {N_{e}{(r^{\prime})}}}^{2^{r^{\prime} - 1} - {N_{e}{(r^{\prime})}}}{A_{in}(j)}}} \rbrack}}$$W_{r_{2}^{\prime}} = {\frac{1}{2^{r^{\prime} - 1} - {2{N_{e}( r^{\prime} )}}}\lbrack {{\sum\limits_{j = {2^{r^{\prime} - 1} + {N_{e}{(r^{\prime})}} + 2^{r^{\prime}}}}^{2^{r^{\prime}} - {N_{e}{(r^{\prime})}} + 2^{r^{\prime}}}{A_{in}(j)}} - {\sum\limits_{j = {{N_{e}{(r^{\prime})}} + 2^{r^{\prime}}}}^{2^{r^{\prime} - 1} - {N_{e}{(r^{\prime})}} + 2^{r^{\prime}}}{A_{in}(j)}}} \rbrack}$  …$W_{r_{(2^{n - r^{\prime}})}^{\prime}} = {\frac{1}{2^{r^{\prime} - 1} - {2{N_{e}( r^{\prime} )}}}{\quad {{{\lbrack {{\sum\limits_{j = {2^{r^{\prime} - 1} + {N_{e}{(r^{\prime})}} + {{(2^{n - r^{\prime} - 1})}2^{r^{\prime}}}}}^{2^{r^{\prime}} - {N_{e}{(r^{\prime})}} + {{({2^{n - r^{\prime}} - 1})}2^{r^{\prime}}}}{A_{in}(j)}} - {\sum\limits_{j = {{N_{e}{(r^{\prime})}} + {{({2^{n - r^{\prime}} - 1})}2^{r^{\prime}}}}}^{2^{r^{\prime} - 1} - {N_{e}{(r^{\prime})}} + {{(2^{n - r^{\prime} - 1})}2^{r^{\prime}}}}{A_{in}(j)}}} \rbrack \mspace{20mu} W_{r^{\prime}}} = {\frac{1}{2^{n - r^{\prime}}}{\sum\limits_{j = 1}^{2^{n - r}}W_{r_{j}^{\prime}}}}};}}}$

repeating as such to extract all capacitor weights remained after ther′^(th) capacitor;

if the capacitor weights of the capacitors after the m^(th) capacitor asdetermined by the process variation have no effect on the monotonicityof the capacitor array, a mismatch error of a capacitor with the weightof less than W_(m′) is negligible, and the weight of the capacitor is anideal weight.

Further, the method further comprises the following steps:

Writing the extracted actual weight into the weight storage circuit;

turning on all the effective capacitors and redundant capacitors toenable the same to participate in the A/D conversion; and

performing the A/D conversion and obtaining a correct output code byusing the actual weights.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a block diagram of a structure of a high-precisionanalog-to-digital converter provided by the present invention.

FIG. 2 is a schematic diagram of a structure of a redundant weightcapacitor array in FIG. 1.

FIG. 3 is a schematic diagram of a flow of extracting an actualcapacitor weight of an analog-to-digital converter based on DNL providedby the present invention.

FIG. 4 is a schematic diagram of a flow of performance improvement ofthe analog-to-digital converter based on DNL provided by the presentinvention.

In the drawings, reference signs are as follows: 11, redundant weightcapacitor array; 12, comparator; 13, code reestablishment circuit; 14,weight storage circuit; and 15, control logic circuit.

DETAILED DESCRIPTION OF THE INVENTION

For a better understanding of the implemented technical means, inventivefeatures, and achieved objects and effects of the present invention, thepresent invention will be further illustrated below in combination withspecific drawings.

As is shown by referring to FIG. 1, the present invention provides ahigh-precision analog-to-digital converter, comprising a redundantweight capacitor array 11, a comparator 12, a code reestablishmentcircuit 13, a weight storage circuit 14 and a control logic circuit 15;wherein

the redundant weight capacitor array 11 receives external input voltagesVin+ and Vin−, generates output voltages Vout+ and Vout− under thecontrol of the control logic circuit 15, supplies the output voltagesVout+ and Vout− to the comparator 12 for comparison, and controls eachbit of capacitor to participate in a voltage addition and subtractionoperation in sequence under the control of the control logic circuit 15according to a comparison result of the comparator 12 to regenerateoutput voltages Vout+ and Vout− which are supplied to the comparator 12for comparison, repeating as such until a last bit of capacitorcompletes the addition and subtraction operation, and the redundantweight capacitor array is combined with the weight storage circuit toimplement digital correction of a capacitor mismatch error, therebypreventing code missing for the analog-to-digital converter;

the comparator 12 compares the output voltages Vout+ and Vout− of theredundant weight capacitor array 11, outputs 1 if Vout+ is more thanVout−, or else, outputs 0;

the code reestablishment circuit 13 calculates an output code of thesuccessive approximation type analog-to-digital converter according toan output result of the comparator 12 and an actual capacitor weightextracted according to DNL in the weight storage circuit 14;

the weight storage circuit 14 stores the actual capacitor weightextracted according to DNL; and

the control logic circuit 15 controls the redundant weight capacitorarray 11 to collect the input voltages in a sampling stage and controlsa corresponding weight capacitor of the redundant weight capacitor array11 to implement the voltage addition and subtraction operation accordingto the output result of the comparator 12 in a conversion stage.

The high-precision analog-to-digital converter provided by the presentinvention employs a capacitor array with redundant weights to enable thedigital correction of a capacitor mismatch error, and with the use ofthe redundant weight, an error brought by the incomplete establishmentof the capacitor array can be withstood, thereby promoting theconversion speed of the analog-to-digital converter; and with themeasurement of the capacitor mismatch error in the present invention,the capacitor mismatch error can be measured without the auxiliarycapacitor array, the auxiliary switch and the control logic, therebyreducing the complexity of the circuit design, and saving layout areaand power consumption, meanwhile, with a digital method in the presentinvention for measuring and correcting the capacitor mismatch, the errormeasurement and correction precision is not limited by a technologicalcondition, thereby improving the measurement and correction precision,and the signal to noise ratio and linearity of the analog-to-digitalconverter are improved by measuring and correcting the capacitormismatch error.

The high-precision analog-to-digital converter provided by the presentinvention has a working principle specifically as follows: Externalinput voltages Vin+ and Vin− are supplied to the redundant weightcapacitor array, which samples input voltages Vin+ and Vin−, generatesoutput voltages Vout+ and Vout− and supplies the output voltages Vout+and Vout− to the comparator for comparison, the redundant weightcapacitor array is controlled in sequence according to a comparatoroutput result to regenerate output voltages Vout+ and Vout− and supplythe output voltages Vout+ and Vout− to the comparator for comparison,repeating as such until a lowest weight bit capacitor completes avoltage addition and subtraction operation, the redundant weightcapacitor array is combined with the weight storage circuit to enabledigital correction for the capacitor mismatch error, thereby preventingcode missing for the analog-to-digital converter; and meanwhile, eachoutput result of the comparator is sent to the code reestablishmentcircuit, which reestablishes a code according to the comparator outputresult and an actual capacitor weight information extracted according toDNL, read from the weight storage circuit, to finally obtain an outputof the analog-to-digital converter.

As a particular embodiment, as is shown by referring to FIG. 2, theredundant weight capacitor array includes n bits of effective capacitors(corresponding to n effective weights) and at least r bits of redundantcapacitors (corresponding to r redundant weights), and the number ofcapacitors included in each bit of the effective capacitor and redundantcapacitor is an integral multiple of 2, wherein an n^(th) bit ofeffective capacitor is C_(n), an (n−1)^(th) bit of effective capacitoris C_(n-1), . . . , a first bit of effective capacitor is C₁, C_(n), isa highest weight effective capacitor with the weight of W_(n), and C₁ isa lowest weight effective capacitor with the weight of W₁; an r^(th) bitof redundant capacitor is C_(r), an (r−1)^(th) bit of redundantcapacitor is C′_(r-1), . . . , a first bit of redundant capacitor isC′₁, C′_(r) is a highest weight redundant capacitor with the weight ofW′_(r), C′₁ is a lowest weight redundant capacitor with the weight ofW′₁, the redundant weight capacitor array may comprise one or more bitsof redundant capacitors from C′_(r), . . . , C′₁ for analog-to-digitalconversion, that is, the redundant weight capacitor array may select pbits of redundant capacitors from the at least r bits of redundantcapacitor for analog-to-digital conversion, and when the redundantweight capacitor array comprises all the capacitors of C′_(r), . . . ,C′₁, p is more than or equal to r, or else, p is less than r; moreover,at least one bit of redundant capacitor is present at each redundantweight, and in a structure of the redundant weight capacitor array asshown in FIG. 2, one bit of the redundant capacitor is present at eachredundant weight. However, the redundant capacitor of each redundantweight is not limited to be one bit and may also be designed asrequired, two or more bits of redundant capacitors are set in oneredundant weight, i.e., two or more redundant capacitors of the sameweight are set in one redundant weight, for example, two bits of firstC′_(r) redundant capacitor and second C′_(r) redundant capacitor withthe same weight can be set in the redundant weight with the weight ofW′_(r); and when two bits of first C′_(r) redundant capacitor and secondC′_(r) redundant capacitor with the same weight can be set in theredundant weight with the weight of W′_(r), the redundant weightcapacitor array comprises r+1 bits of redundant capacitors.

As a particular embodiment, the at least r bits of redundant capacitorC′_(r), . . . , C′₁ in the redundant weight capacitor array may notparticipate in an analog-to-digital conversion process, i.e. a voltageaddition and subtraction operation, under the control of the controllogic circuit. The effective capacitors C_(r), . . . , C₁ correspondingto r bits of redundant capacitor may also not participate in theanalog-to-digital process under the control of the control logiccircuit. But the effective capacitors and the redundant capacitors maynot participate in the analog-to-digital process simultaneously. Thatis, at each weight, at least one of the effective capacitor and theredundant capacitor needs to participate in the analog-to-digitalprocess. When two or more bits of redundant capacitors of the sameweight are set at some redundant weights, one bit of redundant capacitorat a certain redundant weight may be selected at first to participate inthe analog-to-digital conversion in a capacitor weight extractionprocess, and after one capacitor weight extraction period is completed,one bit of residual redundant capacitor is selected from two or morebits of redundant capacitors with the same weight for capacitor weightextraction until the extraction of all the capacitor weights iscompleted. Meanwhile, in the redundant weight capacitor array providedby the present invention, the redundant capacitor is located behind theeffective capacitor of the same weight, thereby possibly guaranteeingthat the conversion process is performed in a descending order of thecapacitor weights to enable the digital correction of the weight error.

As a particular embodiment, the weight storage circuit 14 is used forstoring an actual capacitor weight extracted according to DNL, an n^(th)bit of effective capacitor C_(n) has a weight of W_(n), an (n−1)^(th)bit of effective capacitor C_(n-1) has a weight of W_(n-1), . . . , afirst bit of effective capacitor C₁ has a weight of W₁; and an r^(th)bit of redundant capacitor C′_(r) has a weight of W′_(r), an (r−1)^(th)bit of redundant capacitor C′_(r-1) has a weight of W′_(r-1), . . . , afirst redundant capacitor C′₁ has a weight of W′₁.

As a particular embodiment, in the redundant weight capacitor arrayprovided by the present invention, the number of the least redundantweight as required is determined by a maximum capacitor mismatchingdetermined by a process. If a maximum capacitor mismatch errordetermined by a process and a circuit structure is N_(mismatch) _(_)_(max) LSB, a minimum redundant weight number required by the redundantweight capacitor array is N_(r) _(_) _(min)=1+log₂(N_(mismatch) _(_)_(max)).

As a particular embodiment, the redundant weight capacitor array and thecomparator simultaneously employ a differential structure for connectionor simultaneously employ a single-end structure for connection, therebyenabling structure consistency between the redundant weight capacitorarray and the comparator. Specifically, the redundant weight capacitorarray and the comparator simultaneously employing a differentialstructure for connection or simultaneously employing a single-endstructure for connection specifically refers to that if the differentialstructure is employed, a differential manner is used for connection,with the capacitor array for differential output and the comparator fordifferential input; and if the single-end structure is employed, thesingle-end manner is used for connection, with the capacitor array forsingle-end output and the comparator for single-end input.

As a particular embodiment, the specific circuit structures of thecontrol logic circuit, weight storage circuit and code reestablishmentcircuit in the present invention can be implemented with the existingcircuit structure.

The present invention also provides a DNL-based performance improvementmethod, the method being adapted to the foregoing high-precisionsuccessive approximation type analog-to-digital converter, comprisingthe following steps:

Receiving external input voltages Vin+ and Vin− for sampling, generatingoutput voltages Vout+ and Vout− after sampling and supplying the outputvoltages Vout+ and Vout− to a comparator for comparison, by a redundantweight capacitor array;

comparing the output voltages Vout+ and Vout− by the comparator toobtain a comparison output result;

controlling a corresponding weight capacitor of the redundant weightcapacitor array according to the comparison output result to perform avoltage addition and subtraction operation, regenerating output voltagesVout+ and Vout− and supplying the output voltages Vout+ and Vout− to thecomparator for comparison, by a control logic circuit, repeating as suchuntil a lowest weight bit of capacitor completes the voltage additionand subtraction operation, and implementing digital correction for acapacitor mismatch error by the redundant weight capacitor array incombination with a weight storage circuit to prevent code missing forthe analog-to-digital converter; and

storing each comparison output result, reading an actual capacitorweight extracted according to DNL in the weight storage circuit andcalculating an output code of the successive approximation typeanalog-to-digital converter, by a code reestablishment circuit.

The DNL-based performance improvement method adapted to the foregoinghigh-precision successive approximation type analog-to-digital converterprovided by the present invention employs a capacitor array withredundant weights to enable the digital correction of the capacitormismatch error, and with the use of the redundant weight, an errorbrought by the incomplete establishment of the capacitor array can bewithstood, thereby promoting the conversion speed of theanalog-to-digital converter; and with the measurement of the capacitormismatch error in the present invention, the capacitor mismatch errorcan be measured without the auxiliary capacitor array, the auxiliaryswitch and the control logic, thereby reducing the complexity of thecircuit design, and saving layout area and power consumption, meanwhile,with a digital method in the present invention for measuring andcorrecting the capacitor mismatch, the error measurement and correctionprecision is not limited by a technological condition, thereby improvingthe measurement and correction precision, and the signal to noise ratioand linearity of the analog-to-digital converter are improved bymeasuring and correcting the capacitor mismatch error.

As a particular embodiment, in a sampling stage, the effective capacitorin the redundant weight capacitor array collects the input voltages, theeffective capacitors C_(n), C_(n-1), . . . , C₁ may partially orcompletely participate in the sampling, in case of partial participationin the sampling, all the capacitors from the i^(th) bit to the lowestbit do not participate in the sampling, where i is more than or equal to1; and after the redundant weight capacitor array performs the sampling,the output voltage Vout+ is equal to βVin+, the output voltage Vout− isequal to βVin−, and before all the capacitors participate in the voltageaddition and subtraction operation, the input voltage of the comparatoris as follows: [(V_(out+))−(V_(out−))]₀=[(V_(in+))−(V_(in−))]. In aconversion stage, the control logic circuit controls a correspondingweight capacitor of the redundant weight capacitor array to implementthe voltage addition and subtraction operation according to thecomparator output result, at first, the comparator compares a firstoutput of the output voltages Vout+ and Vout− to obtain a comparisonoutput result D_(n); the control logic circuit controls an effectivecapacitor C_(n) to perform the voltage addition and subtractionoperation according to the comparison output result D_(n) to obtain asecond output of Vout+ and Vout−, i.e. to obtain the output voltage[(V_(out+))−(V_(out−))]_(n) after the operation of the n^(th) effectivecapacitor; and the comparator compares the second output of the outputvoltages Vout+ and Vout− to obtain a comparison output result D_(n-1),repeating as such until a lowest weight bit of capacitor completes thevoltage addition and subtraction operation.

As a preferred embodiment, if the comparison output result D_(n) is 1,it indicates that the output voltage Vout+ is more than the outputvoltage Vout−, the control logic circuit needs to control a capacitorC_(n) corresponding to an n^(th) weight in the redundant weightcapacitor array, and if a voltage of the weight corresponding to C_(n)is subtracted from a previous output voltage, an output voltage of then^(th) bit of effective capacitor C_(n) after the current operation is:

${\lbrack {( V_{{out} +} ) - ( V_{{out} -} )} \rbrack_{n} = {\lbrack {( V_{{out} +} ) - ( V_{{out} -} )} \rbrack_{0} - {\beta {Vref}\frac{W_{n}}{\sum\limits_{k = {i + 1}}^{n}W_{k}}}}};$

if the comparison output result D_(n) is 0, it indicates that the outputvoltage Vout+ is less than the output voltage Vout−, the control logiccircuit needs to control a capacitor C_(n) corresponding to an n^(th)weight in the redundant weight capacitor array, and if a voltage of theweight corresponding to C_(n) is added to a previous output voltage, anoutput voltage of the n^(th) bit of effective capacitor C_(n) after thecurrent operation is:

${\lbrack {( V_{{out} +} ) - ( V_{{out} -} )} \rbrack_{n} = {\lbrack {( V_{{out} +} ) - ( V_{{out} -} )} \rbrack_{0} - {\beta {Vref}\frac{W_{n}}{\sum\limits_{k = {i + 1}}^{n}W_{k}}}}},$

wherein β is a ratio of a sum of sampling capacitors and a sum of allthe capacitors, i.e.

$\beta = {\frac{\sum\limits_{k = {i + 1}}^{n}W_{k}}{{\sum\limits_{k = 1}^{n}C_{k}} + {\sum\limits_{k = 1}^{r}C_{k}^{\prime}}}.}$

Based on the method above, C_(n), C_(n-1), . . . , C_(r), C′_(r),C_(r-1), C′_(r-1), . . . , C₁, C′₁ sequentially perform the voltageaddition and subtraction operation in turn. Specifically, if thecomparison output result D_(j) is 1, it indicates that the outputvoltage Vout+ is more than the output voltage Vout−, the control logiccircuit needs to control a capacitor C_(j) corresponding to a j^(th)weight in the redundant weight capacitor array, and if a voltage of theweight corresponding to C_(j) is subtracted from a previous outputvoltage, for example, when a previous operating capacitor is a capacitorC_(j+1) corresponding to a (j+1)^(th) weight, an output voltage of C_(j)after the current operation is

${\lbrack {( V_{{out} +} ) - ( V_{{out} -} )} \rbrack_{j} = {\lbrack {( V_{{out} +} ) - ( V_{{out} -} )} \rbrack_{j + 1} - {\beta {Vref}\frac{W_{j}}{\sum\limits_{k = {i + 1}}^{n}W_{k}}}}},$

wherein j=1, 2, . . . , n−1; if the comparison output result D_(j) is 0,it indicates that the output voltage Vout+ is less than the outputvoltage Vout−, the control logic circuit needs to control a capacitorC_(j) corresponding to a j^(th) weight in the redundant weight capacitorarray, and if a voltage of the weight corresponding to C_(j) is added toa previous output voltage, for example, when a previous operatingcapacitor is a capacitor C_(j+1) corresponding to a (j+1)^(th) weight,an output voltage of C_(j) after the current operation is

${\lbrack {( V_{{out} +} ) - ( V_{{out} -} )} \rbrack_{j} = {\lbrack {( V_{{out} +} ) - ( V_{{out} -} )} \rbrack_{j + 1} + {\beta {Vref}\frac{W_{j}}{\sum\limits^{n}W}}}},$

wherein j=1, 2, . . . , n−1, repeating as such until a lowest weight bitcapacitor completes the voltage addition and subtraction operation.

As a particular embodiment, the code reestablishment circuit calculatesan output code of the successive approximation type analog-to-digitalconverter according to an output result of the comparator and acapacitor weight in the weight storage circuit, with the steps asfollows:

Reading output results D_(n), D_(n-1), . . . , D_(r), D′_(r), D_(r-1),D′_(r-1), . . . , D₁, D′₁ of the comparator;

reading capacitor weights W_(n), W_(n-1), . . . , W_(r), W′_(r),W_(r-1), W′_(r-1), . . . , W₁, W′₁ in the weight storage circuit; and

calculating an output code, i.e. adding all the output results of thecomparator in terms of weight as follows:D_(out)=W_(n)D_(n)+W_(n-1)D_(n-1)+ . . . +W_(r)D_(r)+W′_(r)D′_(r)+ . . .+W₁D₁+W′₁D′₁.

Due to the presence of the capacitor mismatch in a technologicalprocessing process, the actual weight of the capacitor is not equal tothe ideal weight thereof, resulting in the reduction of the performanceof the analog-to-digital converter, therefore, it is necessary toextract the actual capacitor weight and promote the signal to noiseratio and linearity of the analog-to-digital conversion by using theactual weight. Therefore, as a particular embodiment, as is shown byreferring to FIG. 3, the extracting of the actual capacitor weightextracted according to DNL, stored in the weight storage circuitcomprises the following steps:

S1, setting a capacitor weight initial value in the weight storagecircuit as an ideal weight, specifically comprising the followingsettings:

setting a significant bit weight, with a j^(th) significant bit weightW_(j)=2^(j-1), wherein j=1, 2, . . . , n and

setting a redundant bit weight, with a k^(th) redundant bit weightW′_(k)=W_(k)=2^(k-1), wherein k=1, 2, . . . , r.

S2, turning off all the redundant capacitors so that they do notparticipate in the analog-to-digital conversion, and then performinganalog-to-digital (A/D) conversion according to the set ideal weightvalue to obtain a first output sequence code of the code reestablishmentcircuit;

S3, calculating a first DNL (Differential Nonlinear Error) of theanalog-to-digital converter according to the first output sequence code,where a universal calculation method (for example a code density method)in the industry may be used as a specific method for calculating thefirst DNL sequence, and the detailed description thereof will be omittedherein;

S4, extracting actual weights of capacitors according to the first DNLsequence to obtain the actual weight of the effective capacitor, withthe specific steps as follows:

S41, restoring according to the first DNL sequence to obtain an inputoutput relation of the analog-to-digital converter as follows:

Assuming that the analog-to-digital converter outputs a DNLcorresponding to a digital code 1 as DNL(1), outputs a DNL correspondingto a digital code 2 as DNL(2), . . . , outputs a DNL corresponding to adigital code x as DNL(x), an analog step height corresponding to anx^(th) digital code jump may be obtained according to the DNL asfollows: A(x)=DNL(x)+1, that is, an analog input needs to be added byA(1)=DNL(1)+1LSB for a first output code jump (from 0 to 1), an analoginput needs to be added by A(2)=DNL(2)+1LSB for a second output codejump (from 1 to 2), . . . , an analog input needs to be added byA(x)=DNL(x)+1LSB for an x^(th) output code jump (from x−1 to x), . . . ,and an analog input needs to be added by A(2^(n)−1)=DNL(2^(n)−1)+1LSBfor a (2^(n)−1)^(th) output code jump (from 2^(n)−1 to 2^(n)−1). Assuch, it is possible to further obtain the input output relation of theanalog-to-digital converter as follows:

${{A_{in}(x)} = {{\sum\limits_{j = 1}^{x}{A(j)}} = {x + {\sum\limits_{j = 1}^{x}{{DNL}(j)}}}}},$

wherein A_(in)(x) is an analog-to-digital input voltage incrementcorresponding to a digital code x.

S42, extracting a weight W_(n) of an n^(th) bit of effective capacitorC_(n):

The capacitor C_(n) is a most significant bit capacitor, with a weightof

$W_{n} = {\frac{1}{2^{n - 1} - {2{N_{e}(n)}}}\lbrack {{\sum\limits_{j = {2^{n - 1} + {N_{e}{(n)}}}}^{2^{n} - {N_{e}{(n)}}}{A_{in}(j)}} - {\sum\limits_{j = {N_{e}{(n)}}}^{2^{n - 1} - {N_{e}{(n)}}}{A_{in}(j)}}} \rbrack}$

wherein N_(e)(n) is a number of rejection points determined by processmismatch; assuming a maximum mismatch determined by a process variationis e %, N_(e)(n) is a rounded product of 2^(n)*e % in the calculation ofan n^(th) bit of capacitor weight, i.e. N_(e)(n)=int(2^(n)×e %);

S43, extracting a weight W_(n-1) of an (n−1)^(th) bit of effectivecapacitor C_(n-1) as follows:

The capacitor C_(n-1) is a sub-most significant bit capacitor, with acapacitor weight W_((n-1)) calculated as follows:

$W_{{({n - 1})}_{1}} = {\frac{1}{2^{n - 2} - {2{N_{e}( {n - 1} )}}}\lbrack {{\sum\limits_{j = {2^{n - 2} + {N_{e}{({n - 1})}}}}^{2^{n - 1} - {N_{e}{({n - 1})}}}{A_{in}(j)}} - {\sum\limits_{j = {N_{e}{({n - 1})}}}^{2^{n - 2} - {N_{e}{({n - 1})}}}{A_{in}(j)}}} \rbrack}$$W_{{({n - 1})}_{2}} = {\frac{1}{2^{n - 2} - {2{N_{e}( {n - 1} )}}}\lbrack {{\sum\limits_{j = {2^{n - 2} + {N_{e}{({n - 1})}} + 2^{n - 1}}}^{2^{n - 1} - {N_{e}{({n - 1})}} + 2^{n - 1}}{A_{in}(j)}} - {\sum\limits_{j = {{N_{e}{({n - 1})}} + 2^{n - 1}}}^{2^{n - 2} - {N_{e}{({n - 1})}} + 2^{n - 1}}{A_{in}(j)}}} \rbrack}$$\mspace{20mu} {{W_{({n - 1})} = {\frac{1}{2}\lbrack {W_{{({n - 1})}_{1}} + W_{{({n - 1})}2}} \rbrack}},}$

wherein N_(e)(n−1)=int(2^(n-1)×e %).

S44, extracting a weight W_(m) of an m^(th) bit of effective capacitoras follows:

$\mspace{20mu} {W_{m_{1}} = {\frac{1}{2^{m - 1} - {2{N_{e}(m)}}}\lbrack {{\sum\limits_{j = {2^{m - 1} + {N_{e}{(m)}}}}^{2^{m} - {N_{e}{(m)}}}{A_{in}(j)}} - {\sum\limits_{j = {N_{e}{(m)}}}^{2^{m - 1} - {N_{e}{(m)}}}{A_{in}(j)}}} \rbrack}}$$W_{m\; 2} = {\frac{1}{2^{m - 1} - {2{N_{e}(m)}}}\lbrack {{\sum\limits_{j = {2^{m - 1} + {N_{e}{(m)}} + 2^{m}}}^{2^{m} - {N_{e}{(m)}} + 2^{m}}{A_{in}(j)}} - {\sum\limits_{j = {{N_{e}{(m)}} + 2^{m}}}^{2^{m - 1} - {N_{e}{(m)}} + 2^{m}}{A_{in}(j)}}} \rbrack}$  …$W_{m_{(2^{n - m})}} = {\frac{1}{2^{m - 1} - {2{N_{e}(m)}}}\lbrack {{\sum\limits_{j = {2^{m - 1} + {N_{e}{(m)}} + {{({2^{n - m} - 1})}2^{m}}}}^{2^{m} - {N_{e}{(m)}} + {{({2^{n - m} - 1})}2^{m}}}{A_{in}(j)}} - {\sum\limits_{j = {{N_{e}{(m)}} + {{({2^{n - m} - 1})}2^{m}}}}^{2^{m - 1} - {N_{e}{(m)}} + {{({2^{n - m} - 1})}2^{m}}}{A_{in}(j)}}} \rbrack}$$\mspace{20mu} {{W_{m} = {\frac{1}{2^{n - m}}{\sum\limits_{j = 1}^{2^{n - m}}W_{mj}}}};}$

S45, repeating as such to extract all capacitor weights remained afterthe m^(th) capacitor;

if the capacitor weights of the capacitors after the m^(th) capacitor asdetermined by the process variation have no effect on the monotonicityof the capacitor array, a mismatch error of a capacitor with the weightof less than W_(m) is negligible, and the weight of the capacitor is anideal weight.

S5, turning off the effective capacitors corresponding to all theredundant capacitors so that they do not participate in the A/Dconversion and then performing A/D conversion to obtain a second outputsequence code of the code reestablishment circuit;

S6, calculating a second DNL sequence of the analog-to-digital converteraccording to the second output sequence code; and

S7, extracting an actual capacitor weight according to the second DNLsequence to obtain an actual weight of the redundant capacitor, wherethe method is the same as that for extracting the effective capacitorweight, specifically comprising the following steps:

S71, restoring according to the second DNL sequence to obtain an inputoutput relation of the analog-to-digital converter as follows:

Assuming that the analog-to-digital converter outputs a DNLcorresponding to a digital code 1 as DNL′(1), outputs a DNLcorresponding to a digital code 2 as DNL′(2), . . . , outputs a DNLcorresponding to a digital code x as DNL′(x), an analog step heightcorresponding to an x^(th) digital code jump may be obtained accordingto the DNL as follows: A′(x)=DNL′(x)+1, that is an analog input needs tobe added by A′(1)=DNL′(1)+1LSB for a first output code jump (from 0 to1), an analog input needs to be added by A′(2)=DNL′(2)+1LSB for a secondoutput code jump (from 1 to 2), . . . , an analog input needs to beadded by A′(x)=DNL′(x)+1LSB for an x^(th) output code jump (from x−1 tox), . . . , and an analog input needs to be added byA′(2^(n)−1)=DNL′(2^(n)−1)+1LSB for a (2^(n)−1)^(th) output code jump(from 2^(n)−2 to 2^(n)−1). As such, it is possible to further obtain theinput output relation of the analog-to-digital converter as follows:

${{A_{in}^{\prime}(x)} = {{\sum\limits_{j = 1}^{x}{A^{\prime}(j)}} = {x + {\sum\limits_{j = 1}^{x}{{DNL}^{\prime}(j)}}}}},$

wherein A′_(in)(x) is an analog input voltage increment corresponding toa digital code x.

S72, extracting a weight W_(r′) of an r′^(th) redundant capacitor asfollows:

$\mspace{20mu} {W_{r_{1}^{\prime}} = {\frac{1}{2^{r^{\prime} - 1} - {2{N_{e}( r^{\prime} )}}}\lbrack {{\sum\limits_{j = {2^{r^{\prime} - 1} + {N_{e}{(r^{\prime})}}}}^{2^{r^{\prime}} - {N_{e}{(r^{\prime})}}}{A_{in}(j)}} - {\sum\limits_{j = {N_{e}{(r^{\prime})}}}^{2^{r^{\prime} - 1} - {N_{e}{(r^{\prime})}}}{A_{in}(j)}}} \rbrack}}$$W_{r_{2}^{\prime}} = {\frac{1}{2^{r^{\prime} - 1} - {2{N_{e}( r^{\prime} )}}}\lbrack {{\sum\limits_{j = {2^{r^{\prime} - 1} + {N_{e}{(r^{\prime})}} + 2^{r^{\prime}}}}^{2^{r^{\prime}} - {N_{e}{(r^{\prime})}} + 2^{r^{\prime}}}{A_{in}(j)}} - {\sum\limits_{j = {{N_{e}{(r^{\prime})}} + 2^{r^{\prime}}}}^{2^{r^{\prime} - 1} - {N_{e}{(r^{\prime})}} + 2^{r^{\prime}}}{A_{in}(j)}}} \rbrack}$  …$W_{r_{(2^{n - r^{\prime}})}^{\prime}} = {\frac{1}{2^{r^{\prime} - 1} - {2{N_{e}( r^{\prime} )}}}\lbrack {{\sum\limits_{j = {2^{r^{\prime} - 1} + {N_{e}{(r^{\prime})}} + {{(2^{n - r^{\prime} - 1})}2^{r^{\prime}}}}}^{2^{r^{\prime}} - {N_{e}{(r^{\prime})}} + {{({2^{n - r^{\prime}} - 1})}2^{r^{\prime}}}}{A_{in}(j)}} - {\sum\limits_{j = {{N_{e}{(r^{\prime})}} + {{({2^{n - r^{\prime}} - 1})}2^{r^{\prime}}}}}^{2^{r^{\prime} - 1} - {N_{e}{(r^{\prime})}} + {{(2^{n - r^{\prime} - 1})}2^{r^{\prime}}}}{A_{in}(j)}}} \rbrack}$$\mspace{20mu} {{W_{r^{\prime}} = {\frac{1}{2^{n - r^{\prime}}}{\sum\limits_{j = 1}^{2^{n - r}}W_{r_{j}^{\prime}}}}};}$

S73, repeating as such to extract all capacitor weights remained afterthe r′^(th)capacitor;

and if the capacitor weights of the capacitors after the m^(th)capacitor as determined by the process variation have no effect on themonotonicity of the capacitor array, a mismatch error of a capacitorwith the weight of less than W_(m′) is negligible, and the weight of thecapacitor is an ideal weight.

As a preferred embodiment, when two or more bits of redundant capacitorsof the same weight are set in some redundant weights, one bit ofredundant capacitor in a certain redundant weight may be selected atfirst to participate in the analog-to-digital conversion in a capacitorweight extraction process, and after one capacitor weight extractionperiod is completed, one bit of residual redundant capacitor is selectedfrom two or more bits of redundant capacitors with the same weight forcapacitor weight extraction until the extraction of all the capacitorweights is completed.

As a particular embodiment, as is shown by referring to FIG. 4, theextracted actual capacitor weight is used to improve the performance ofthe analog-to-digital conversion, which further comprises the followingsteps:

Writing the extracted actual weight into the weight storage circuit;

turning on all the effective capacitors and redundant capacitors toenable the same to participate in the A/D conversion; and

performing the A/D conversion and obtaining a correct output code byusing the actual weights.

The foregoing merely provides the embodiments of the present invention,but is not intended to thereby limit the patent scope of the presentinvention. Any equivalent structures made by utilizing the specificationand accompanying drawings of the present invention and applied to otherrelevant technical fields directly or indirectly likewise fall under thescope of patent protection of the present invention.

What is claimed is:
 1. A high-precision analog-to-digital converter,comprising a redundant weight capacitor array, a comparator, a codereestablishment circuit, a weight storage circuit and a control logiccircuit; wherein the redundant weight capacitor array receives externalinput voltages Vin+ and Vin−, generates output voltages Vout+ and Vout−under the control of the control logic circuit, supplies the outputvoltages Vout+ and Vout− to the comparator for comparison, and controlseach bit of capacitor to participate in a voltage addition andsubtraction operation in sequence under the control of the control logiccircuit according to a comparison result of the comparator to regenerateoutput voltages Vout+ and Vout− which are supplied to the comparator forcomparison, repeating as such until a last bit of capacitor completesthe voltage addition and subtraction operation, and the redundant weightcapacitor array is combined with the weight storage circuit to implementdigital correction of a capacitor mismatch error, thereby preventingcode missing for the analog-to-digital converter; the comparatorcompares the output voltages Vout+ and Vout− of the redundant weightcapacitor array, outputs 1 if Vout+ is more than Vout−, or else, outputs0; the code reestablishment circuit calculates an output code of thesuccessive approximation type analog-to-digital converter according toan output result of the comparator and an actual capacitor weightextracted according to DNL in the weight storage circuit; the weightstorage circuit stores the actual capacitor weight extracted accordingto DNL; and the control logic circuit controls the redundant weightcapacitor array to collect the input voltages in a sampling stage andcontrols a corresponding weight capacitor of the redundant weightcapacitor array to implement the voltage addition and subtractionoperation according to the output result of the comparator in aconversion stage.
 2. The high-precision analog-to-digital converteraccording to claim 1, wherein the redundant weight capacitor arraycomprises n bits of effective capacitors and at least r bits ofredundant capacitors, and the number of capacitors included in each bitof the effective capacitor and redundant capacitor is an integralmultiple of 2, wherein an n^(th) bit of effective capacitor is C_(n), an(n−1)^(th) bit of effective capacitor is C_(n-1), . . . , a first bit ofeffective capacitor is C₁, C_(n) is a highest weight effective capacitorwith the weight of W_(n), C₁ is the lowest weight effective capacitorwith the weight of W₁; and an r^(th) bit of redundant capacitor isC′_(r), an (r−1)^(th) bit of redundant capacitor is C′_(r-1), . . . , afirst bit of redundant capacitor is C′₁, C′_(r) is a highest weightredundant capacitor with the weight of W′_(r), C′₁ is a lowest weightredundant capacitor with the weight of W′₁, the redundant weightcapacitor array may comprise one or more bits of redundant capacitorsfrom C′_(r), . . . , C′₁ for analog-to-digital conversion, and at leastone bit of redundant capacitor is present at each redundant weight. 3.The high-precision analog-to-digital converter according to claim 2,wherein the redundant capacitors are located behind the effectivecapacitors having the same weight as the redundant capacitors.
 4. Thehigh-precision analog-to-digital converter according to claim 2, whereina maximum capacitor mismatch error determined by a process and a circuitstructure is N_(mismatch) _(_) _(max) LSB, and a minimum redundantweight number required by the redundant weight capacitor array is N_(r)_(_) _(min)=1+log₂(N_(mismatch) _(_) _(max)).
 5. The high-precisionanalog-to-digital converter according to claim 1, wherein the redundantweight capacitor array and the comparator simultaneously employ adifferential structure for connection or simultaneously employ asingle-end structure for connection.
 6. A DNL-based performanceimprovement method, the method being adapted to a high-precisionanalog-to-digital converter, comprising the following steps: receivingexternal input voltages Vin+ and Vin− for sampling, generating outputvoltages Vout+ and Vout− after sampling and supplying the outputvoltages Vout+ and Vout− to a comparator for comparison, by a redundantweight capacitor array; comparing the output voltages Vout+ and Vout− bythe comparator to obtain a comparison output result; controlling acorresponding weight capacitor of the redundant weight capacitor arrayaccording to the comparison output result to perform a voltage additionand subtraction operation, regenerating output voltages Vout+ and Vout−and supplying the output voltages Vout+ and Vout− to the comparator forcomparison, by a control logic circuit, repeating as such until a lowestweight bit of capacitor completes the voltage addition and subtractionoperation, and implementing digital correction for a capacitor mismatcherror by the redundant weight capacitor array in combination with aweight storage circuit to prevent code missing for the analog-to-digitalconverter; and storing each comparison output result, reading an actualcapacitor weight extracted according to DNL in the weight storagecircuit and calculating an output code of the successive approximationtype analog-to-digital converter, by a code reestablishment circuit. 7.The DNL-based performance improvement method according to claim 6,wherein after the redundant weight capacitor array performs sampling,the output voltage Vout+ is equal to βVin+, the output voltage Vout− isequal to βVin−, and the comparator compares a first output of the outputvoltages Vout+ and Vout− to obtain a comparison output result D_(n); thecontrol logic circuit controls an effective capacitor C_(n) to performthe voltage addition and subtraction operation according to thecomparison output result D_(n) to obtain a second output of Vout+ andVout−; and the comparator compares the second output of the outputvoltages Vout+ and Vout− to obtain a comparison output result D_(n-1),repeating as such until a lowest weight bit of capacitor completes thevoltage addition and subtraction operation.
 8. The DNL-based performanceimprovement method according to claim 7, wherein if the comparisonoutput result D_(n) is 1, an output voltage of an n^(th) effectivecapacitor after operation is:${\lbrack {( V_{{out} +} ) - ( V_{{out} -} )} \rbrack_{n} = {\lbrack {( V_{{out} +} ) - ( V_{{out} -} )} \rbrack_{0} - {\beta {Vref}\frac{W_{n}}{\sum\limits_{k = {i + 1}}^{n}W_{k}}}}};$if the comparison output result D_(n) is 0, an output voltage of then^(th) effective capacitor after operation is:${\lbrack {( V_{{out} +} ) - ( V_{{out} -} )} \rbrack_{n} = {\lbrack {( V_{{out} +} ) - ( V_{{out} -} )} \rbrack_{0} - {\beta {Vref}\frac{W_{n}}{\sum\limits_{k = {i + 1}}^{n}W_{k}}}}};$and C_(n), C_(n-1), . . . , C_(r), C′_(r), C_(r-1), C′_(r-1), . . . ,C₁, C′₁ sequentially perform the voltage addition and subtractionoperation in turn, wherein β is a ratio of a sum of sampling capacitorsto a sum of all the capacitors;$\beta = {\frac{\sum\limits_{k = {i + 1}}^{n}W_{K}}{{\sum\limits_{k = 1}^{n}C_{k}} + {\sum\limits_{k = 1}^{r}C_{k}^{\prime}}}.}$9. The DNL-based performance improvement method according to claim 6,wherein the code reestablishment circuit calculates the output code ofthe successive approximation type analog-to-digital converter with aformula as follows:D _(out) =W _(n) D _(n) +W _(n-1) D _(n-1) + . . . +W _(r) D _(r) +W′_(r) D′ _(r) + . . . +W ₁ D ₁ +W′ ₁ D′ ₁ wherein W_(n), W_(n-1), . . . ,W_(r), W′_(r), . . . , W₁, W′₁ are capacitor weights stored in theweight storage circuit, and D_(n), D_(n-1), . . . , D_(r), D′_(r), D₁,D′₁ are comparison output results of the comparator.
 10. The DNL-basedperformance improvement method according to claim 6, wherein extractionof the actual capacitor weight extracted according to DNL, stored in theweight storage circuit, comprises the following steps: setting acapacitor weight initial value in the weight storage circuit as an idealweight; turning off all the redundant capacitors and then performinganalog-to-digital (A/D) conversion to obtain a first output sequencecode of the code reestablishment circuit; calculating a first DNLsequence of the analog-to-digital converter according to the firstoutput sequence code; extracting actual weights of effective capacitorsaccording to the first DNL sequence; turning off the effectivecapacitors corresponding to all the redundant capacitors and thenperforming A/D conversion to obtain a second output sequence code of thecode reestablishment circuit; calculating a second DNL sequence of theanalog-to-digital converter according to the second output sequencecode; and extracting actual weights of the redundant capacitorsaccording to the second DNL sequence.
 11. The DNL-based performanceimprovement method according to claim 10, wherein the setting acapacitor weight initial value in the weight storage circuit as an idealweight specifically comprises: setting a significant bit weight, with aj^(th) significant bit weight W_(j)=2^(j-1), wherein j=1, 2, . . . , n;and setting a redundant bit weight, with a k^(th) redundant bit weightW′_(k)=W_(k)=2^(k-1), wherein k=1, 2, . . . , r.
 12. The DNL-basedperformance improvement method according to claim 10, wherein theextracting actual weights of effective capacitors according to the firstDNL sequence specifically comprises the following steps: restoringaccording to the first DNL sequence to obtain an input output relationof the analog-to-digital converter as follows:${{A_{in}(x)} = {{\sum\limits_{j = 1}^{x}{A(j)}} = {x + {\sum\limits_{j = 1}^{x}{{DNL}(j)}}}}},$wherein A_(in)(x) is an analog input voltage increment corresponding toa digital code x; extracting a weight of an n^(th) effective capacitoras follows:${W_{n} = {\frac{1}{2^{n - 1} - {2{N_{e}(n)}}}\lbrack {{\sum\limits_{j = {2^{n - 1} + {N_{e}{(n)}}}}^{2^{n} - {N_{e}{(n)}}}{A_{in}(j)}} - {\sum\limits_{j = {N_{e}{(n)}}}^{2^{n - 1} - {N_{e}{(n)}}}{A_{in}(j)}}} \rbrack}},$wherein N_(e)(n) is a number of rejection points determined by a processmismatch; assuming a maximum mismatch determined by a process variationis e %, N_(e)(n) is a rounded product of 2^(n)*e % in the calculation ofan n^(th) bit of capacitor weight, i.e. N_(e)(n)=int(2^(n)×e %);extracting a weight W_(n-1) of an (n−1)^(th) bit of effective capacitoras follows:$W_{{({n - 1})}_{1}} = {\frac{1}{2^{n - 2} - {2{N_{e}( {n - 1} )}}}\lbrack {{\sum\limits_{j = {2^{n - 2} + {N_{e}{({n - 1})}}}}^{2^{n - 1} - {N_{e}{({n - 1})}}}{A_{in}(j)}} - {\sum\limits_{j = {N_{e}{({n - 1})}}}^{2^{n - 2} - {N_{e}{({n - 1})}}}{A_{in}(j)}}} \rbrack}$$W_{{({n - 1})}_{2}} = {\frac{1}{2^{n - 2} - {2{N_{e}( {n - 1} )}}}\lbrack {{\sum\limits_{j = {2^{n - 2} + {N_{e}{({n - 1})}} + 2^{n - 1}}}^{2^{n - 1} - {N_{e}{({n - 1})}} + 2^{n - 1}}{A_{in}(j)}} - {\sum\limits_{j = {{N_{e}{({n - 1})}} + 2^{n - 1}}}^{2^{n - 2} - {N_{e}{({n - 1})}} + 2^{n - 1}}{A_{in}(j)}}} \rbrack}$$\mspace{20mu} {{W_{({n - 1})} = {\frac{1}{2}\lbrack {W_{{({n - 1})}_{1}} + W_{{({n - 1})}2}} \rbrack}},}$wherein N_(e)(n−1)=int(2^(n-1)×e %); extracting a weight W_(m) of anm^(th) bit of effective capacitor as follows:$\mspace{20mu} {W_{m_{1}} = {\frac{1}{2^{m - 1} - {2{N_{e}(m)}}}\lbrack {{\sum\limits_{j = {2^{m - 1} + {N_{e}{(m)}}}}^{2^{m} - {N_{e}{(m)}}}{A_{in}(j)}} - {\sum\limits_{j = {N_{e}{(m)}}}^{2^{m - 1} - {N_{e}{(m)}}}{A_{in}(j)}}} \rbrack}}$$W_{m_{2}} = {\frac{1}{2^{m - 1} - {2{N_{e}(m)}}}\lbrack {{\sum\limits_{j = {2^{m - 1} + {N_{e}{(m)}} + 2^{m}}}^{2^{m} - {N_{e}{(m)}} + 2^{m}}{A_{in}(j)}} - {\sum\limits_{j = {{N_{e}{(m)}} + 2^{m}}}^{2^{m - 1} - {N_{e}{(m)}} + 2^{m}}{A_{in}(j)}}} \rbrack}$  …$W_{m_{(2^{n - m})}} = {\frac{1}{2^{m - 1} - {2{N_{e}(m)}}}\lbrack {{\sum\limits_{j = {2^{m - 1} + {N_{e}{(m)}} + {{({2^{n - m} - 1})}2^{m}}}}^{2^{m} - {N_{e}{(m)}} + {{({2^{n - m} - 1})}2^{m}}}{A_{in}(j)}} - {\sum\limits_{j = {{N_{e}{(m)}} + {{({2^{n - m} - 1})}2^{m}}}}^{2^{m - 1} - {N_{e}{(m)}} + {{({2^{n - m} - 1})}2^{m}}}{A_{in}(j)}}} \rbrack}$$\mspace{20mu} {{W_{m} = {\frac{1}{2^{n - m}}{\sum\limits_{j = 1}^{2^{n - m}}W_{mj}}}};}$repeating as such to extract all capacitor weights remained after them^(th) capacitor; if the capacitor weights of the capacitors after them^(th) capacitor as determined by the process variation have no effecton the monotonicity of the capacitor array, a mismatch error of acapacitor with the weight of less than W_(m) is negligible, and theweight of the capacitor is an ideal weight.
 13. The DNL-basedperformance improvement method according to claim 10, wherein theextracting actual weights of redundant capacitors according to thesecond DNL sequence specifically comprises the following steps:restoring according to the second DNL sequence to obtain an input outputrelation of the analog-to-digital converter as follows:${{A_{in}^{\prime}(x)} = {{\sum\limits_{j = 1}^{x}{A^{\prime}(j)}} = {x + {\sum\limits_{j = 1}^{x}{{DNL}^{\prime}(j)}}}}},$wherein A′_(in)(x) is an analog input voltage increment corresponding toa digital code x; extracting a weight W_(r′) of an r′^(th) redundantcapacitor as follows:$\mspace{20mu} {W_{r_{1}^{\prime}} = {\frac{1}{2^{r - 1} - {2{N_{e}( r^{\prime} )}}}\lbrack {{\sum\limits_{j = {2^{r - 1} + {N_{e}{(r^{\prime})}}}}^{2^{r} - {N_{e}{(r^{\prime})}}}{A_{in}(j)}} - {\sum\limits_{j = {N_{e}{(r^{\prime})}}}^{2^{r - 1} - {N_{e}{(r^{\prime})}}}{A_{in}(j)}}} \rbrack}}$$W_{r_{2}^{\prime}} = {\frac{1}{2^{r - 1} - {2{N_{e}( r^{\prime} )}}}\lbrack {{\sum\limits_{j = {2^{r - 1} + {N_{e}{(r^{\prime})}} + 2^{r^{\prime}}}}^{2^{r} - {N_{e}{(r^{\prime})}} + 2^{r^{\prime}}}{A_{in}(j)}} - {\sum\limits_{j = {{N_{e}{(r^{\prime})}} + 2^{r^{\prime}}}}^{2^{r - 1} - {N_{e}{(r^{\prime})}} + 2^{r^{\prime}}}{A_{in}(j)}}} \rbrack}$  …$W_{r^{\prime}{(2^{n - r^{\prime}})}} = {\frac{1}{2^{r^{\prime} - 1} - {2{N_{e}( r^{\prime} )}}}\lbrack {{\sum\limits_{j = {2^{r^{\prime} - 1} + {N_{e}{(r^{\prime})}} + {{({2^{n - r^{\prime}} - 1})}2^{r^{\prime}}}}}^{2^{r^{\prime}} - {N_{e}{(r^{\prime})}} + {{(2^{n - r^{\prime} - 1})}2^{r^{\prime}}}}{A_{in}(j)}} - {\sum\limits_{j = {{N_{e}{(r^{\prime})}} + {{({2^{n - r^{\prime}} - 1})}2^{r^{\prime}}}}}^{2^{r^{\prime} - 1} - {N_{e}{(r^{\prime})}} + {{({2^{n - r^{\prime}} - 1})}2^{r^{\prime}}}}{A_{in}(j)}}} \rbrack}$$\mspace{20mu} {{W_{r^{\prime}} = {\frac{1}{2^{n - r^{\prime}}}{\sum\limits_{j = 1}^{2^{n - r^{\prime}}}W_{r_{j}^{\prime}}}}};}$repeating as such to extract all capacitor weights remained after ther′^(th) capacitor; if the capacitor weights of the capacitors after them^(th) capacitor as determined by the process variation have no effecton the monotonicity of the capacitor array, a mismatch error of acapacitor with the weight of less than W_(m′) is negligible, and theweight of the capacitor is an ideal weight.
 14. The DNL-basedperformance improvement method according to claim 10, wherein the methodfurther comprises the following steps: writing the extracted actualweight into the weight storage circuit; turning on all the effectivecapacitors and redundant capacitors to enable the same to participate inthe A/D conversion; and performing the A/D conversion and obtaining acorrect output code by using the actual weights.